1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) arrays and, in particular, to an alternate metal virtual ground (AMG) EPROM array that utilizes self-aligned trench isolation for achieving bit line isolation between select transistors without compromising memory performance.
2. Discussion of the Prior Art
Both R. Kazerounian et al., "Alternate Metal Virtual Ground EPROM Array Implemented In A 0.8 Micron Process For Very High Density Applications", IEDM, p. 311, 1991, and B. Eitan et al., "Alternate Metal Virtual Ground (AMG)--A New Scaling Concept For Very High-Density EPROMs", IEEE Electron Device Letters, Vol. 12, p. 450, 1991, disclose an AMG EPROM architecture that transfers the layout scaling limitation of the array from the metal pitch to the polysilicon pitch by strapping alternate diffusion bit lines and by employing select transistors. Utilizing this array architecture, an EPROM cell size of 2.56 .mu.m.sup.2 with 0.8 .mu.m layout rules can be realized for high density memory applications, e.g. 4 Mbits and beyond.
A further advantage associated with the AMG array architecture is that, by utilizing MOS select transistors, drain turn-on induced punch-through can be minimized.
The MOS select transistors in a conventional AMG array are isolated utilizing a conventional LOCOS isolation scheme. As shown in FIG. 1, with 0.8 .mu.m layout rules, bit line-to-bit line spacing is only 0.8 .mu.m, which is much less than the isolation spacing of 1.2 .mu.m required to form a minimum-sized field oxide island. Furthermore, as can be seen from the FIG. 2 layout, poly1 to field oxide island misalignment, the field oxide rounding effect at concave corners, and field oxide thinning with reduced nitride spacing prevent simple scaling of an AMG array below 0.8 .mu.m design rules.
Recently, Wolstenholme et al. proposed a scheme that utilizes programmed EPROM cells to achieve bit line isolation. As shown in FIG. 3, to implement the Wolstenholme et al. isolation scheme, the MOS select transistors utilized in the conventional AMG architecture are replaced by EPROM cells which are the same as the EPROM cells used in the memory array. Along each select line Sel and Sel, every other EPROM cell is programmed to a high threshold voltage (V.sub.th) state to achieve bit line to bit line isolation. These programmed EPROM cells are depicted in FIG. 3 with a solid dot between the control gate and the floating gate.